1. Field of the Invention
The present invention relates generally to semiconductor devices and manufacturing methods thereof, and more specifically, to a semiconductor device having a vertical field effect transistor and a manufacturing method thereof.
2. Description of the Background Art
Conventionally, SGTs (Surrounding Gate Transistors) are known as vertical field effect transistors. They are disclosed, for example, in an article entitled "High Performance CMOS Surrounding Gate Transistor (SGT) for Ultra High Density LSIs", IEDM88 Technical Digest, pp 222-225. FIG. 64 is a plan view showing a conventional SGT disclosed therein. FIG. 65 is a cross sectional view showing the SGT in FIG. 64 taken along line X--X. Referring to FIGS. 64 and 65, the conventional SGT includes a silicon substrate 301, a silicon pillar 301a formed in a prescribed region on the silicon substrate 301 and extending in a direction vertical to a main surface of the silicon substrate 301, a P well 302 formed on the main surface of the silicon substrate 301 and having a prescribed depth, a pair of n type source regions 303 formed in the part of the main surface of the silicon substrate adjacent to the silicon pillar 301a, an n type drain region 304 formed on the top end of the silicon pillar 301a, and a gate electrode 306 formed on the outer peripheral surface of the silicon pillar 301a with a gate oxide film 305 therebetween. The sidewalls of the silicon pillar 301a positioned between the source region 303 and the drain region 304 constitute the channel region of the SGT. More specifically, the channel length L of the SGT is defined by the height of the silicon pillar 301a, and the channel width of the SGT is defined by the outer peripheral length of the silicon pillar 301a. In this manner, in the conventional SGT, the sidewalls of the silicon pillar 301a can be used as the channel region, area occupied by the elements can be reduced as compared to a conventional planar type transistor. In other words, the SGT is an element suitable for high density integration.
The conventional SGT however suffers from the following disadvantage.
As the length t of the silicon pillar 301a in a direction along the main surface of the silicon substrate 301 shown in FIG. 65 is shortened with increase of the integration densities of devices, it will be difficult to control the threshold voltage of the SGT by channel doping. This phenomenon is described in detail, for example, in IEEE TRANSACTION OF ELECTRON, VOL. ED-30, No. 10, October 1983 CHAPTER III (pp. 1247-1250). As described above, in the conventional SGT, it will be difficult control its threshold voltage by channel doping with the sizes of elements being reduced, impeding accurate control of the threshold voltage as a result.
A conventional method of controlling the threshold voltage by changing the material of a gate electrode has been proposed. Such a method is disclosed in Physics of Semiconductor Devices SECOND EDITION by S. M. Sze pp. 363-397 (Table 3 (p. 396)). In this document, a proposed method controls the threshold voltage by using a gate electrode of Au or the like rather than a conventional gate electrode of polycrystalline silicon. According to this method, it is principly possible to control the threshold voltage.
However, Au used for the gate electrode can contaminate environment in a clean room free of heavy metals which is suitable for manufacturing silicon semiconductors. Furthermore, a gate electrode of Au is less suitable for mass production as compared to a gate electrode of polysilicon. On top of that, it is technically difficult to manufacture a gate electrode of Au or the like.
As described above, the conventional method of controlling the threshold voltage using a gate electrode formed of Au or the like is principly possible, but still encountered with various problems in practice. As a result, it has been difficult to accurately control the threshold voltage of an SGT in practice when the sizes of its elements are reduced.